Due to a recent tendency of continuously reducing size and thickness of electronic devices, a high-density packaging technology has been increasingly advanced along with fine processing and integration of semiconductor elements.
Generally, a wire bonding method using metal wires and a flip chip bonding method using solder balls have been adopted as a method for bonding a wiring substrate and a semiconductor element in a semiconductor element package.
The wire bonding method is advantageous in that it may achieve low-cost packaging with respect to semiconductor elements having a small number of pads, whereas it is necessary to reduce the diameter of each wire due to increasingly reduced pitches between pads of semiconductor elements; hence, wire breaks may cause a problem of a low yield rate in an assembling process.
Compared to the wire bonding method, the flip chip bonding method achieves high-speed signal transmission between semiconductor elements and wiring substrates, whereas due to an increasing number of pads of semiconductor elements and due to increasingly reduced pitches between pads of semiconductor elements, solder bumps undergo weak bonding strengths, which may lead to the formation of cracks at bonded points and the frequent occurrence of bonding defects.
Recently, a semiconductor element incorporating technology using packages with wiring substrates, including supporting substrates, incorporating semiconductor elements has been developed as a high-density packaging technology which realizes further integration and highly-advanced functionality in semiconductor devices and which results in many advantages such as thin packages, low cost, adaptability to high frequencies, low stress bonding, and improvement of electromigration property.
FIG. 37 shows the structure of a semiconductor element incorporated substrate disclosed in Patent Literature 1. The semiconductor element incorporated substrate includes an insulating resin substrate 1, a wire 2 formed on one surface thereof, and an electronic circuit. Herein, bumps 3 are formed for the purpose of bonding the electronic circuit, wherein a semiconductor element 4 is embedded inside the insulating resin substrate 1 such that the bump 3 will be connected to the wire 2.
FIG. 38 shows the structure of a semiconductor element incorporated substrate disclosed in Patent Literature 2. The semiconductor element incorporated substrate includes an insulating layer 6 incorporating a semiconductor element 5, and a wiring structure 7 connected to the semiconductor element 5, wherein a reinforcing structure 8 is embedded in the insulating layer 6.